The present invention relates generally to semiconductor devices, and more particularly to fin-type field-effect transistors (finFETs).
To meet the continued demand for scale-reduced integrated circuits having increased speeds, it is necessary to design transistors that have higher drive currents with smaller dimensions. The development of fin-type field-effect transistors (finFETs) provides transistors with increased channel widths that achieve drive currents that are proportional to the channel widths. However, the width quantization effect of the device, i.e., the effective device width, is typically required to be an integral of a single fin perimeter. In addition, static random-access memory (SRAM) applications typically include both n-type finFETs (nFETs) and p-type finFETs (pFETs), where the nFET has a greater drive current, i.e., a non-integral ratio, with respect to the pFET. The non-integral ratio between the nFET and the pFET is difficult to achieve due to the quantization effect mentioned above. Recent efforts to address the non-integral ratio have included attempts to adjust the vertical height of the semiconductor fins. However, conventional methods for adjusting the semiconductor fin height during the fabrication process has proven to create fm-height and gate stack topographical variations.